1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly relates to a vertical type Insulated Gate Bipolar Transistor (hereinafter referred to simply as "IGBT") having a planar gate structure.
2. Description of the Background Art
Generally, IGBT has been utilized widely as an element for controlling a motor or for switching an inverter or the like. IGBT is a voltage drive element having both of a low saturation voltage property of the bipolar transistor and a high speed switching property of the MOSFET. IGBT is characterized by that the loss of driving power and the loss at ON/OFF switching are small. Recently, IGBT has been used widely since it has a device structure to allow ON voltage to be reduced by miniaturizing MOSFET formed at the chip surface and improving the degree of integration of MOSFET.
A vertical type IGBT having a planar gate structure is mentioned here as one example of a conventional IGBT, and the structure thereof is hereinafter described. FIG. 15 is a cross sectional view showing an n channel IGBT having a conventional planar gate structure.
With reference to FIG. 15, an n drift region 1 is formed at a side of a first main surface 14a of a semiconductor substrate 14, and a p base region 2 is selectively formed in n drift region 1. An n emitter region 3 is selectively formed in p base region 2. A region which is sandwiched between n drift region 1 and n emitter region 3, located within p base region 2, and reaches the first main surface 14a is referred to as a channel formation region 4. A gate dielectric layer 5 is formed on the first main surface 14a to cover channel formation region 4. Gate dielectric layer 5 extends from a portion over n emitter region 3 to a portion over n drift region 1.
P base region 2 and n emitter region 3 are short-circuited by a metal electrode layer (emitter electrode) 8. P base region 2 and metal electrode layer 8 as well as n emitter region 3 and metal electrode layer 8 are in ohmic contact with each other. A p collector region 10 is formed at a side of a second main surface 14b of semiconductor substrate 14. A metal electrode layer (collector electrode) 11 is formed on the second main surface 14b so that metal electrode layer 11 is in ohmic contact with p collector region 10.
An operation of an n channel IGBT having the above structure is described. Four processes, specifically a transient process from a cut-off (OFF) state to a conduction (ON) state, a steady state, a transient process from the ON state to the OFF state, are respectively described below.
(1) Transient process from OFF state to ON state
Positive (+) voltage is applied to gate electrode 6 while voltage which is relatively positive to the voltage at emitter electrode 8 is applied to collector electrode 11. Accordingly, a channel inverted to become n type is formed at channel formation region 4 located in p base region 2. Through this n channel, the electron as one of the carriers is injected from n emitter region 3 into n drift region 1, and the electron flows toward p collector region 10. When the electron reaches p collector region 10, the hole as one of carriers is injected from p collector region 10 into n drift region 1. The hole flows toward n emitter region 3 to which relatively negative voltage is applied, and the hole reaches a place where the n channel contacts with n drift region 1. This process is referred to as a storage process, and the time required for this process is referred to as a turn-on delay time (td (on)). The loss of electric power in this process is extremely small and negligible.
Enough carriers are thereafter stored according to the potential applied between emitter electrode 8 and collector electrode 11, and a low-resistance state referred to as conductivity modulation due to a pair of electron-hole occurs. Accordingly, the turn-on operation completes. This process is called a rise process, and the time required for this process is called rise time (t(rise)). The loss of electric power in this process is relatively large.
(2) Steady state
The steady state after completion of the turn-on operation is called ON state, and the voltage when current of 100A/cm.sup.2 flows is called ON voltage. The power loss in this state is called ON loss or steady loss, and expressed by the product of forward voltage drop caused by a resistance component and conducting current. The power loss in ON state is generally exceedingly large. The resistance component in the ON state is determined by the sum of respective resistance components existing at the current path of the device or between emitter electrode 8 and collector electrode 11. The current path of the device is added to the cross sectional view of IGBT in FIG. 15 and shown in FIG. 16 together.
Referring to FIG. 16, C, E and G in this figure respectively represent terminals of electrodes of the collector, emitter, and gate. Further, Ic, Ih, and Ie respectively represent collector current of IGBT, hole current flowing from n drift region 1 into p base region 2, and electron current flowing from n drift region 1 into n emitter region 3 through channel formation region 4. As shown in FIG. 16, the total resistance component R affecting the ON voltage can be expressed by the following equation. EQU R=Rcn+Rn+Rch+Ra+R.sub.JFET +Rd+Rdiode+Rs+Rcp
In the equation above, Rcn is contact resistance between n emitter region 3 and metal electrode layer 8, Rn is resistance of n emitter region 3, Rch is resistance of the channel, Ra is resistance of the storage layer, R.sub.JFET is a resistance component due to JEFT (Junction-FET) effect, Rd is resistance of n drift region 1, Rdiode is forward voltage drop of the diode between p collector region 10 and n drift region 1, Rs is resistance of p collector region 10, and Rcp is the contact resistance between p collector region 10 and metal electrode layer 11.
(3) Transient process from ON state to OFF state
OFF state is caused by applying a voltage of at most the threshold voltage such as negative (-) voltage to gate electrode 6. When the potential at gate electrode 6 is the threshold voltage or less, the n channel formed in ON state disappears. Accordingly, supply of electrons from n emitter region 3 to n drift region 1 is stopped. This process is referred to as a storage process, and the time required for this process is called storage time or turn off delay time (td (OFF)). The power loss during this process is extremely small and negligible. Since the supply of electrons is stopped, the density of electrons gradually decreases from a region in the vicinity of n emitter region 3. Accordingly, the holes injected into n drift region 1 for maintaining an electrically neutral condition also decreases.
Since p base region 2 and n drift region 1 are in a reverse bias state, a depletion layer begins to expand at an interface between p base region 2 and n drift region 1. The depletion layer has a thickness corresponding to a voltage applied between collector electrode 11 and emitter electrode 8. This process is called fall process, the time required for this process is called fall time, and the power loss during this process is called fall loss. The power loss during this period is equivalent to or larger than the turn on loss and the steady state loss. Holes among carriers outside the depletion region pass through the depletion region, pass through a p.sup.+ contact region having high concentration in p base region 2 which is electrically short-circuited with n emitter region, and reach emitter electrode layer 8. All of the carriers thus disappear and the turn-off complete. This process is called a tail process, the time required for this process is called tail time (t (tail)), and the power loss in these process is called tail loss. The power loss during this process is extremely large.
(4) OFF state
The steady state after completion of the turn-off is referred to as OFF state. The power loss expressed by the product of the leakage current in this state and the voltage between collector electrode 11 and emitter electrode 8 is extremely small compared with other power losses, and is negligible.
Various power losses occur in respective processes of conduction/cut-off in the conventional IGBT as described above. In order to achieve a high performance of IGBT, reduction of any one of these losses is desired. Inventors of this application turn the attention to the power loss in the ON state having an extremely large value compared with other losses. It is enough to decrease ON voltage to reduce the power loss in ON state.
In the conventional planar gate type IGBT shown in FIG. 15, ON voltage can be somewhat reduced by scaling down IGBT. The reason is that each component of IGBT is reduced mainly in lateral direction with respect to FIG. 16 by the scaling down, resulting in reduction of the resistance component. However, the scaling down is limited and sufficient reduction of ON voltage is difficult.
Another method of reducing ON voltage is to decrease the concentration of p base region 2. However, the latch-up phenomenon could occur by the reduction of the concentration of p base region 2. When the latch-up phenomenon happens, electrons are directly injected from n emitter region 3 into p base region 2 if the voltage drop when hole current Ih flows from n drift region 1 to p base region 2 exceeds the built-in voltage of the npn bipolar transistor constituted by n emitter region 3, p base region 2 and n drift region 1. Once the latch-up occurs, the current flowing through IGBT due to the voltage applied to gate electrode 6 cannot be controlled and IGBT could be damaged.